The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present. Design of High-Performance CMOS Voltage-Controlled Oscillators noise, analyzes the impact of the supply and substrate noise on the oscillator phase noise, and suggests techniques for reducing the jitter due to the supply and substrate noise.
The primary audience for Design of High-Performance CMOS Voltage-Controlled Oscillators is research workers and design engineers who concentrate on high performance communication circuits. This work will also be of interest to analog circuit designers.
eBook Design of High-Performance CMOS Voltage-Controlled Oscillators